Iteration Mapping: Loop Software Pipelining on an XIMD

The multiple instruction streams, low synchronization cost and synchronous nature of the XIMD (variable instruction stream, multiple data stream) architecture create an opportunity for a new architecture-compiler interface. As an extension to the VLIW (Very Long Instruction Word) architecture, the XIMD can exploit all VLIW scheduling techniques but these do not take full advantage of the unique features of the XIMD. A new loop scheduling method for the XIMD, Iteration Mapping, is proposed that can exceed the performance of VLIW loop scheduling techniques on an XIMD. The medium-grained parallelism between loop iterations has been selected as the target for the first XIMD compiler implementation. This paper discusses how the relationship between the characteristics of loops and the architecture affect scheduling, presents the Iteration Mapping scheduling technique, presents performance data for loops scheduled using this new technique and compares it with recent results on software pipelining for the VLIW, and demonstrates the applicability of the technique for loop-intensive code. The weighted harmonic mean of the speedup for 4 functional units on the first fourteen Livermore Loops is currently 3.5, and the weighted harmonic mean of the speedup for selected loops that Iteration Mapping is particularly well suited for on 16 functional units is 14.5, more than 90% of linear speedup. The concepts behind Iteration Mapping are clean and understandable, leading to a compiler that is straight-forward, fast, and easy to implement.